`include "defines.svh"
`include "CP0Defines.svh"
`include "CacheDefines.svh"
module MEM_MEM2 (
input logic clk,
input logic reset,

input logic MEM_MEM2_Flush,
input logic MEM_MEM2_Stall,

input logic MEM_CP0Wr,
input logic MEM_DMRd,
input logic [31:0]MEM_PC,
input logic [31:0]MEM_NPC,
input logic [31:0]MEM_Instr,
input logic [2:0]MEM_DMOp,
input logic [31:0]MEM_Data_Writed,
input logic [2:0]MEM_Reg_Writed_End,        
input logic MEM_DMWr,
input logic [31:0]MEM_ALU_Out,
input logic [4:0]MEM_RW_End,          
input logic MEM_MemToRegWr,
input logic [1:0]MEM_Data_To_Reg_Sel,
input logic MEM_IsBranch,
input logic MEM_Immjump,
input logic MEM_isDelaySlot,
input ExceptionType MEM_ExceptionTypeEnd,

output logic MEM2_CP0Wr,
output logic MEM2_DMRd,
output logic [31:0]MEM2_PC,
output logic [31:0]MEM2_NPC,
output logic [31:0]MEM2_Instr,
output logic [2:0]MEM2_DMOp,
output logic [31:0]MEM2_Data_Writed,
output logic [2:0]MEM2_Reg_Writed,   
output logic MEM2_DMWr,
output logic [31:0]MEM2_ALU_Out,
output logic [4:0]MEM2_RW,        
output logic MEM2_MemToRegWr,
output logic [1:0]MEM2_Data_To_Reg_Sel,
output logic MEM2_IsBranch,
output logic MEM2_Immjump,
output logic MEM2_isDelaySlot,
output ExceptionType MEM2_ExceptionType
);
    always_ff @(posedge clk,negedge reset)
    begin
        if(!reset||MEM_MEM2_Flush)begin
            MEM2_PC <= 32'b0;
            MEM2_NPC <= 32'b0;
            MEM2_Instr <= 32'b0;
            MEM2_DMOp <= 3'b0;
            MEM2_Data_Writed <= 32'b0;
            MEM2_DMWr <= 1'b0;
            MEM2_ALU_Out <= 32'b0;
            MEM2_RW <= 5'b0;
            MEM2_MemToRegWr <= 1'b0;
            MEM2_Data_To_Reg_Sel <= 2'b0;
            MEM2_IsBranch<=1'b0;
            MEM2_Immjump<=1'b0;
            MEM2_CP0Wr<=1'b0;
            MEM2_DMRd<=1'b0;
            MEM2_ExceptionType<=`NoException;
            MEM2_Reg_Writed <= 3'b0;
            MEM2_isDelaySlot<=1'b0;
        end
        else if(!MEM_MEM2_Stall)begin
            MEM2_CP0Wr<=MEM_CP0Wr;
            MEM2_DMRd<=MEM_DMRd;
            MEM2_PC <= MEM_PC;
            MEM2_NPC <= MEM_NPC;
            MEM2_Instr <= MEM_Instr;
            MEM2_DMOp <= MEM_DMOp;
            MEM2_Data_Writed <= MEM_Data_Writed;
            MEM2_DMWr <= MEM_DMWr;
            MEM2_ALU_Out <= MEM_ALU_Out;
            MEM2_RW <= MEM_RW_End;
            MEM2_MemToRegWr <= MEM_MemToRegWr;
            MEM2_Data_To_Reg_Sel <= MEM_Data_To_Reg_Sel;
            MEM2_IsBranch<=MEM_IsBranch;
            MEM2_Immjump<=MEM_Immjump;
            MEM2_ExceptionType<=MEM_ExceptionTypeEnd;
            MEM2_Reg_Writed <= MEM_Reg_Writed_End;
            MEM2_isDelaySlot<=MEM_isDelaySlot;
        end 
        else   
            ; 
    end

endmodule